The present invention relates to a semiconductor device having insulated gate type non-volatile non-changeable semiconductor memory elements (hereinafter abbreviated as "non-volatile memory elements"), and more particularly, to a semiconductor device having two or more circuits including non-volatile memory elements.
A semiconductor device for use in a microcomputer is a typical example of semiconductor devices having two or more circuits constructed of insulated gate semiconductor memory elements on a single semiconductor substrate. This semiconductor device contains, on a single semiconductor substrate, a central processing unit (hereinafter abbreviated as "CPU"), an input/output section (hereinafter abbreviated as "I/O" section) including an input circuit for inputting information contents from an external circuit and an output circuit for outputting information contents to an external circuit, a RAM section having random access memory elements ("RAM" elements) for reading or writing information contents therefrom or thereinto, and a ROM section having read-only semiconductor memory elements ("ROM" elements) for reading information contents therefrom. The CPU generates control signals for controlling the I/O section, RAM section and ROM section, and also contains an instruction decoder. The instruction decoder has a function of generating control signals by reading information contents in the RAM elements and the ROM elements forming the RAM section and the ROM section, respectively. The semiconductor memory elements forming this instruction decoder achieve the same function and have the same structure as the ROM elements forming the ROM section.
In order to write information contents in the ROM elements forming the above-mentioned instruction decoder and the ROM section, the prior art has used a method of writing during a manufacturing process of a semiconductor device. However, this type of semiconductor device had a shortcoming. After a semiconductor device has once left a manufacturing process, even if it is desired to rewrite memory contents in the memory elements therein, it is definitely impossible.
As one countermeasure for the above-mentioned shortcoming, a ROM device has employed non-volatile memory elements as semiconductor memory elements. Among the non-volatile memory elements, an MNOS element is known in which carriers are stored at a boundary surface between a silicon oxide film and a silicon nitride film. In the MNOS element, electrical writing and electrical erasing can be achieved. On the other hand, a non-volatile memory element having a floating gate electrode is also known which has been generally called FAMOS element, up to now. In this FAMOS element, electrical writing and erasing by irradiation of ultra-violet rays can be achieved. However, recently, an element has been developed with a floating gate electrode in which electrical writing and electrical erasing can be achieved. In this element, lower-energy electrons are made to pass through an oxide film under a floating gate electrode by making use of Fowler-Nordheim tunnels. The above-mentioned element having a floating gate electrode in which electrical erasing can be achieved, will be hereinafter called an "F-N element", for convenience.
The above-described non-volatile memory elements in a ROM section eliminate the previous shortcoming that it is not possible to rewrite the memory contents in the memory elements in a semiconductor device which has once left a manufacturing process. However, there would still remain a shortcoming in the case of rewriting the information contents of semiconductor memory elements in a CPU. They must be written during a manufacturing process which is similar to the above-described case.
As one solution for eliminating this shortcoming, the CPU may also have non-volatile memory elements similar to a ROM device. However, a resultant device would have the same type of non-volatile memory elements in a CPU and in a ROM section. Therefore semiconductor device would have the following shortcoming. If ultra-violet erasable FAMOS elements are employed in both the CPU and the ROM section, the erasing of information contents would be effected simultaneously in both the CPU and the ROM section. Hence it would be difficult to preserve the information contents in either the CPU or the ROM section and to erase information contents only in the other. Whereas, if MNOS elements or F-N elements, in which electrical erasing can be achieved, are employed in both of the CPU and the ROM section, upon erasing, it would be possible to preserve information contents in one of the CPU and the ROM section and to erase information contents in only the other. However, in the event that a large number of these electrically erasable non-volatile memory elements are arrayed in a matrix form, in order to effect electrical erasing and electrical writing, it would be necessary to connect at least one insulated gate type semiconductor element for selection to each MNOS element on the like. Therefore, the semiconductor device would have a shortcoming that it is not suitable to form a memory device having a large memory capacity by arraying the memory elements in a matrix form.